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| SI8401DB Vishay Siliconix P-Channel 20-V (D-S) MOSFET PRODUCT SUMMARY VDS (V) -20 FEATURES ID (A) -4.9 -4.1 rDS(on) (W) 0.065 @ VGS = -4.5 V 0.095 @ VGS = -2.5 V D TrenchFETr Power MOSFET D New MICRO FOOTr Chipscale Packaging Reduces Footprint Area Profile (0.62 mm) and On-Resistance Per Footprint Area D Pin Compatible to Industry Standard Si3443DV APPLICATIONS D PA, Battery and Load Switch D Battery Charger Switch D PA Switch S MICRO FOOT Bump Side View 3 D D 2 Backside View 8401 xxx G Device Marking: 8401 xxx = Date/Lot Traceability Code S 4 G 1 D P-Channel MOSFET Ordering Information: SI8401DB-T1 SI8401DB-T1--E3 (Lead Free) ABSOLUTE MAXIMUM RATINGS (TA = 25_C UNLESS OTHERWISE NOTED) Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (TJ = 150_C)a Pulsed Drain Current continuous Source Current (Diode Conduction)a Maximum Power Dissipationa Operating Junction and Storage Temperature Range Package Reflow Conditionsb VPR IR/Convection TA = 25_C TA = 70_C TA = 25_C TA = 70_C Symbol VDS VGS ID IDM IS PD TJ, Tstg 5 secs Steady State -20 "12 Unit V -4.9 -3.9 -10 -2.5 2.77 1.77 -55 to 150 215/245c 220/250c -3.6 -2.8 A -2.5 1.47 0.94 W _C _C THERMAL RESISTANCE RATINGS Parameter Maximum J Mi Junction-to-Ambienta ti t A bi t Maximum Junction-to-Foot (drain) t v 5 sec Steady State Steady State Symbol RthJA RthJF Typical 35 72 16 Maximum 45 85 20 Unit _C/W C/W Notes a. Surface Mounted on 1" x 1" FR4 Board. b. Refer to IPC/JEDEC (J-STD-020A), no manual or hand soldering. c. Package reflow conditions for lead-free. Document Number: 71674 S-40384--Rev. F, 01-Mar-04 www.vishay.com 1 SI8401DB Vishay Siliconix SPECIFICATIONS (TJ = 25_C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Currenta Drain-Source On-State Drain Source On State Resistancea Forward Transconductancea Diode Forward Voltagea VGS(th) IGSS IDSS ID(on) rDS( ) DS(on) gfs VSD VDS = VGS, ID = -250 mA VDS = 0 V, VGS = "12 V VDS = -20 V, VGS = 0 V VDS = -20 V, VGS = 0 V, TJ = 70_C VDS v -5 V, VGS = -4.5 V VGS = -4.5 V, ID = -1 A VGS = -2.5 V, ID = -1 A VDS = -10 V, ID = -1 A IS = -1 A, VGS = 0 V -5 0.057 0.080 6 -0.73 -1.1 0.065 0.095 -0.45 -0.9 "100 -1 -5 V nA mA A W S V Symbol Test Condition Min Typ Max Unit Dynamicb Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time Qg Qgs Qgd td(on) tr td(off) tf trr IF = - A, di/dt = 100 A/ms VDD = -10 V, RL = 10 W ID ^ -1 A, VGEN = -4.5 V, RG = 6 W VDS = -10 V, VGS = -4.5 V, ID = -1 A 11 2.1 2.9 17 28 88 60 25 45 135 90 ns 17 nC Notes a. Pulse test; pulse width v 300 ms, duty cycle v 2%. b. Guaranteed by design, not subject to production testing. TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) 10 Output Characteristics VGS = 5 thru 2.5 V 10 Transfer Characteristics 8 I D - Drain Current (A) I D - Drain Current (A) 2V 6 8 6 4 4 TC = 125_C 2 25_C -55_C 2 1.5 V 0 0 2 4 6 8 10 VDS - Drain-to-Source Voltage (V) www.vishay.com 0 0.0 0.5 1.0 1.5 2.0 2.5 VGS - Gate-to-Source Voltage (V) Document Number: 71674 S-40384--Rev. F, 01-Mar-04 2 SI8401DB Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) 0.15 On-Resistance vs. Drain Current 1500 Capacitance r DS(on) - On-Resistance ( W ) 0.12 VGS = 2.5 V 0.09 VGS = 4.5 V C - Capacitance (pF) 1200 Ciss 900 0.06 600 Coss 300 Crss 0.03 0.00 0 1 2 3 4 5 6 7 0 0 4 8 12 16 20 ID - Drain Current (A) VDS - Drain-to-Source Voltage (V) 10 V GS - Gate-to-Source Voltage (V) VDS = 10 V ID = 1 A Gate Charge 1.6 On-Resistance vs. Junction Temperature VGS = 4.5 V ID = 1 A 8 1.4 rDS(on) - On-Resiistance (Normalized) 6 1.2 4 1.0 2 0.8 0 0 4 8 12 16 20 Qg - Total Gate Charge (nC) 0.6 -50 -25 0 25 50 75 100 125 150 TJ - Junction Temperature (_C) Source-Drain Diode Forward Voltage 10 0.30 On-Resistance vs. Gate-to-Source Voltage r DS(on) - On-Resistance ( W ) 0.24 ID = 1 A 0.18 I S - Source Current (A) TJ = 150_C 1 0.12 TJ = 25_C 0.06 0.1 0.0 0.00 0.2 0.4 0.6 0.8 1.0 1.2 0 1 2 3 4 5 6 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Document Number: 71674 S-40384--Rev. F, 01-Mar-04 www.vishay.com 3 SI8401DB Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Threshold Voltage 0.4 0.3 V GS(th) Variance (V) 0.2 0.1 0.0 20 -0.1 -0.2 -50 ID = 250 mA 60 Power (W) 80 Single Pulse Power, Juncion-To-Ambient 40 -25 0 25 50 75 100 125 150 0 0.001 0.01 0.1 Time (sec) 1 10 TJ - Temperature (_C) Normalized Thermal Transient Impedance, Junction-to-Ambient 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10-1 1 Square Wave Pulse Duration (sec) Notes: PDM t1 t2 1. Duty Cycle, D = 2. Per Unit Base = RthJA = 72_C/W 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted t1 t2 10 100 600 Normalized Thermal Transient Impedance, Junction-to-Foot 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10-1 Square Wave Pulse Duration (sec) 1 10 www.vishay.com 4 Document Number: 71674 S-40384--Rev. F, 01-Mar-04 SI8401DB Vishay Siliconix PACKAGE OUTLINE MICRO FOOT: 4-BUMP (2 X 2, 0.8-mm PITCH) 4 O 0.30 X 0.31 Note 3 Solder Mask O X 0.40 e A A2 A1 Bump Note 2 b Diamerter e Recommended Land S Silicon E e 8401 XXX e D Mark on Backside of Die S NOTES (Unless Otherwise Specified): 1. 2. 3. 4. Laser mark on the silicon die back, coated with a thin metal. Bumps are Eutectic solder 63/57 Sn/Pb. (Sn 3.8 Ag, 0.7 Cu for Pb-free bumps) Non-solder mask defined copper landing pad. The flat side of wafers is oriented at the bottom. MILLIMETERS* Dim A A1 A2 b D E e S Min 0.600 0.260 0.340 0.370 1.520 1.520 0.750 0.370 INCHES Min 0.0236 0.0102 0.0134 0.0146 0.0598 0.0598 0.0295 0.0146 Max 0.650 0.290 0.360 0.410 1.600 1.600 0.850 0.380 Max 0.0256 0.0114 0.0142 0.0161 0.0630 0.0630 0.0335 0.0150 * Use millimeters as the primary measurement. Document Number: 71674 S-40384--Rev. F, 01-Mar-04 www.vishay.com 5 |
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